1. Field of the Invention
The present invention relates to a semiconductor device and a process for production thereof. More particularly, the present invention is intended to provide a semiconductor device containing a precision capacitive element and a process for production thereof.
2. Description of the Related Arts
Electronic machines and equipment are becoming smaller in size and lighter in weight, and are improving in performance and expanding in functions. This movement is accelerating the trend toward integrating linear or analog circuits (essential for AV machines and communication instruments) with digital circuits into a single semiconductor device (LSI). These circuits need precision capacitive elements, which are conventionally of DFC (Double Poly Capacitor) type or MIM (Metal-Insulator-Metal) type. The former type is composed of two polysilicon layers and one capacitive insulating film held between them. The latter type is composed of two metal layers and one capacitive insulating film held between them.
A capacitive element of DPC type is disclosed in Japanese Patent Laid-open No. HEI 9(1997)-36313. It has capacitive electrodes constructed of polysilicon layers which are semiconductor layers. Therefore, a small depletion layer occurs in the capacitive electrode itself no matter how large the amount of impurities added to polysilicon may be. The depletion layer thus formed fluctuates in width depending on the potential applied across the capacitive electrodes. This leads to fluctuation in capacitive value. Therefore, the capacitive element of DPC type does not suit circuits which need a very high precision.
In contrast, the capacitive element of MIM type, in which the capacitive electrodes are made of metal, does not permit a depletion layer to occur. Therefore, it offers the advantage of keeping a constant capacitive value regardless of potential across the electrodes. For this reason, it is common practice to use capacitive elements of MIM type for precision analog circuits.
A capacitive element of MIM type and a process for production thereof are disclosed in, for example, Japanese Patent Laid-open No. HEI 8(1996)-181282.
The process is illustrated in FIGS. 3(a) to 3(d).
On a semiconductor substrate 41 is deposited a silicon oxide film 42. On the silicon oxide film 42 is deposited a first metal layer 43. From this metal layer 43 are formed a lower electrode 43a and a wiring 43b by patterning through a mask of resist pattern (not shown) formed by photolithography. See FIG. 3(a).
On the semiconductor substrate 41 is deposited an oxide film 44 by a plasma CVD method. On the oxide film 44 is formed an SOG (Spin On Glass) film 45 by spin coating. The SOG film 45 undergoes etch-back by RIE (reactive ion etching) to such an extent that the underlying oxide film 44 is exposed. As a result, the SOG film 45 partly remains on the vertical step of the first metal layer 43, thereby moderating the slope angle of the step. Furthermore, an oxide film 46 is formed on the semiconductor substrate 41 by a plasma CVD method. See FIG. 3(b).
A resist pattern (not shown) having an opening above the lower electrode 43a is formed by photolithography. Using this resist pattern as a mask, etching by RIE is performed on the oxide film 44 and 46 so as to form an opening 47 through which the surface of the lower electrode 43a is exposed. On the semiconductor substrate 41 is deposited a plasma nitride film 48 which functions as the capacitive insulating film. See FIG. 3(c).
A resist pattern (not shown) having an opening above the wiring 43b is formed by photolithography. Using this resist pattern as a mask, etching by RIE is performed on the oxide film 44 and 46 and the plasma nitride film so as to form an opening 49 through which the surface of the wiring 43b is exposed. See FIG. 3(d).
On the semiconductor substrate 41 is further deposited a second metal layer, which is subsequently undergoes patterning using a resist pattern (not shown) as a mask formed by photolithography, so that an upper electrode 50a is formed above the lower electrode 43a and a wiring 50b is formed above the wiring 43b. In this way there are obtained a capacitive element 52 of MIM structure and a wiring 51 of laminate structure, the former being composed of the lower electrode 43a, the capacitive insulating film 46 and the upper electrode 50a, and the latter being composed of the wiring 43b and the wiring 50b. See FIG. 3(d).
In addition, Japanese Patent Laid-open No. HEI 9(1997)-92786 discloses a capacitive element of MIM type and a process for production thereof, as explained in the following.
The process is illustrated in FIGS. 4(a) to 4(f).
On a semiconductor substrate 60 is deposited a first metal layer 61, which is subsequently patterned as desired. Then, on the semiconductor substrate 60 is deposited an insulating layer 62, the surface of which is subsequently planarized by CMP (Chemical Mechanical Polish) method or the like. See FIG. 4(a).
The insulating layer 62 is etched using a resist pattern (not shown) as a mask formed by photolithography to such an extent that the first metal layer 51 is exposed, so that openings 63a and 63b are formed. See FIG. 4(b).
On the semiconductor substrate 60 is entirely deposited a thin dielectric film 64, which functions as a capacitive insulating film afterward. On the thin dielectric film 64 is deposited by photolithography a resist pattern 65 which has an opening above the opening 63b. This opening functions as a connection for the metal wiring layer. See FIG. 4(c).
The dielectric film 64 undergoes etching through the resist pattern 65 as a mask, so that the first metal layer 61 is exposed at the bottom of the opening 63b. See FIG. 4(d).
On the entire surface of the semiconductor substrate 60 is deposited a second metal layer 65. See FIG. 4(e).
The second metal layer 65 is patterned into a desired form through a resist pattern (not shown) as a mask formed by photolithography, so as to form an upper electrode 65a and a wiring 65b. In this way there is formed a capacitive element 66 of MIM structure composed of the lower electrode 61, the dielectric film 64 and the upper electrode 65a, and also there is formed the wiring 65b connected to the lower electrode 61. See FIG. 4(f).
The conventional capacitive elements of MIM structure as mentioned above, however, have posed the following problems as recent semiconductor devices are required to have finer fabrication and faster operating speeds. That is, as semiconductor devices have came to have finer fabrication and faster operating speeds, the metal wiring has become multi4ayered. And in the circuits containing analog elements such as capacitive elements, three to six layers of wiring is now required.
The process of forming multi-layered wiring requires that each layer is planarized sufficiently. The result of failure in planarization is that the subsequent step to finely pattern the metal layer or to form a small opening in the interlayer film has to be carried out on an uneven surface. Photolithography on an uneven surface suffers a decrease in focusing margin, which makes it difficult to form fine and precision patterns and openings. Making each layer flat is a key factor in the process of forming multilayered wiring. One way to meet this requirement is to planarize the insulating film between metal wiring layers by CMP method.
The disadvantage of the above-mentioned conventional process for producing capacitive elements is that the opening 47 or 63a (for a capacitive element to be formed therein) causes the surface of the upper electrode 50a or 65a to have unevenness which is originated in the steps of the underlying interlayer insulating film. Such steps present difficulties in the fine patterning of the upper electrode 50a or 65a and also in the pattering of multilayered wiring formed on the electrodes.
The present invention was completed in order to address the above-mentioned problems. Accordingly, it is an object of the present invention to provide a semiconductor device having a precision capacitive element (with a structure suitable for microfabrication) and a process for producing the same.
In according with one aspect of the present invention, there is provided a semiconductor device comprises a first insulating film which is formed on a semiconductor substrate and has a groove whose bottom does not reach said semiconductor substrate, and a capacitive element which is composed of a lower electrode of a first metal layer which is embedded in said groove, a capacitive insulating film of a second insulating film formed on said lower electrode, and an upper electrode of a second metal layer formed in a region where both said lower electrode and said capacitive insulating film are formed.
In according with another aspect of the present invention, there is provided a semiconductor device comprises; an element formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate containing said element, and having at least one opening whose bottom reaches said element and at least one groove whose bottom does not reach said element, a contact plug of a first metal layer embedded in said opening, a lower electrode or wiring layer of the first metal layer embedded in the groove, a capacitive insulating film of a second insulating film formed on said lower electrode, an upper electrode of the second metal layer which is formed in a region where both the lower electrode and the capacitive insulating film are formed, and a metal wiring of the second metal layer formed on said contact plug.
In according with still another aspect of the present invention, there is provided a process for producing a semiconductor device, said process comprises the steps of: depositing a first insulating film on a semiconductor substrate, forming in said first insulating film a groove whose bottom does not reach said semiconductor substrate, depositing a first metal layer on the first insulating film containing said groove, selectively etching said first metal layer to form a lower electrode only in said groove, depositing a second insulating film on said first insulating film containing said lower electrode, patterning said second insulating film to form a capacitive insulating film on said lower electrode, depositing a second metal layer on said capacitive insulating film, and selectively etching said second metal layer to form an upper electrode in a region where both the lower electrode and the capacitive insulating film are formed.
In according with still another aspect of the present invention, there is provided a process for producing a semiconductor device, said process comprises a step of: forming an element on a semiconductor substrate, depositing a first insulating film on said element, forming in said first insulating film at least one opening whose bottom reaches said element and at least one groove whose bottom does not reach said element, depositing a first metal layer on the first insulating film containing said opening and said groove, selectively etching said first metal layer to form a contact plug in said opening and a lower electrode or wiring layer in said groove, depositing a second insulating film on the first insulating film containing said contact plug, lower electrode and wiring layer, patterning said second insulating film to form a capacitive insulating film on said lower electrode, depositing a second metal layer on said capacitive insulating layer, and selectively etching said second metal layer to form an upper electrode in a region where both the lower electrode and the capacitive insulating film are formed, and to form a metal wiring on said contact layer.